1. Field of the Invention
The invention relates to a latch circuit comprising:
a differential amplifier constituted by first and second transistors, each having a first and a second main electrode and a control electrode, the first main electrodes being interconnected to a first junction and the control electrodes being coupled to data signal input terminals for receiving a data signal to be latched,
biasing means coupled to the first junction for generating a bias current in the first junction,
first and second load impedances inserted between a first supply terminal and first and second output terminals, respectively, for delivering a latched output signal,
a flip-flop comprising third and fourth transistors each having a first and a second main electrode and a control electrode, the first main electrodes being interconnected to a second junction, the second main electrode of the third transistor and the control electrode of the fourth transistor being coupled to the first output terminal and the second main electrode of the fourth transistor and the control electrode of the third transistor being coupled to the second output terminal,
switching means for coupling, in response to a clock signal, the second main electrodes of the first and second transistors to the first and second output terminals, respectively, the switching means being constituted by fifth and sixth transistors each having a first and a second main electrode and a control electrode, the control electrodes being coupled to a clock signal input for receiving the clock signal, the first main electrodes of the fifth and sixth transistors being coupled to the second main electrodes of the first and second transistors, respectively, and the second main electrodes of the fifth and sixth transistors to the first and second output terminals, respectively.
In the present description and claims the first main electrode, the second main electrode and the control electrode of a transistor correspond to the emitter, collector and base, respectively, when bipolar transistors are used, and to the source, drain and gate, respectively, when unipolar transistors are used.
2. Description of the Related Art
A latch circuit of this type is known from "An 8-bit 100-MHz Full-Nyquist Analog-to-Digital Converter", IEEE Journal Of Solid-State Circuits, Vol. 23, No. 6, December 1988, pp. 1334-1344, FIG. 12. In this prior-art latch circuit the transistors are of the bipolar NPN type. If the clock signal is high, the fifth and sixth transistors of the switching means are rendered conductive and connect the collectors of the first and second transistors of the differential amplifier to the first and second load impedances. An amplified data signal is then present on the first and second output terminals. At that moment the flip-flop is not active because the second junction is maintained currentless by means of two further transistors whose bases are biased by means of the inverse clock signal.
If the clock signal is low, the fifth and sixth transistors are rendered non-conductive so that the connections between the collectors of the first and second transistors of the differential amplifier and the first and second load impedances are interrupted. A further change of the data signal then no longer has an influence on the voltage difference across the first and second output terminals. The latch circuit comprises two further transistors whose collectors are connected to the second junction, the bases to an input terminal for receiving an inverted clock signal and whose emitters, in a first or second emitter junction respectively, are connected to the emitter of the fifth or sixth transistor respectively. Concurrently with the drop of the clock signal, the two further transistors are rendered conductive by the inverted clock signal so that the second junction is connected to the collectors of the first and second transistors of the differential amplifier. The bias current of the biasing means now flows through the first and second transistors to the second junction so that the flip-flop is triggered again and the differential voltage across the first and second output terminals is amplified and latched regeneratively.
A disadvantage of this prior-art latch circuit is that the first or second emitter junction may become currentless for a longer period of time if the sign of the differential voltage on the data signal input terminals is not inverted. During that period of time, the voltage on the emitter junction concerned may flow away. If, subsequently, the sign of the differential voltage is inverted, the relevant transistor of the differential amplifier will become conductive and supply current to the emitter junction. As a result of the presence of parasitic capacitances in the emitter junction, it will take some time before the capacitances are charged and the differential voltage across the first and second output terminals is brought into agreement with the sign inversion of the data signal. With high clock signal frequencies it may happen, in dependence on the magnitude of the data signal, that the sign inversion of the differential voltage across the first and second output terminals has not yet taken place the moment the clock signal becomes low again and the circuit assumes the latching mode. An erroneous decision will then be made.